Improvements to a restricted out-of-order processor

Dnr:

SNIC 2015/6-162

Type:

SNAC Small

Principal Investigator:

Trevor Carlson

Affiliation:

Uppsala universitet

Start Date:

2015-11-23

End Date:

2017-12-01

Primary Classification:

10201: Datavetenskap (= Datalogi)

Webpage:

Allocation

Abstract

In-order processors are very efficient at general purpose processing (W/MIPS) but unfortunately have very low performance. The Load Slice Core (LSC) microarchitecture has improved the performance of in-order cores by using them as a baseline, but by created a restricted out-of-order processor that optimizes the memory hierarchy instead of instruction-level parallelism (ILP). This work adepts to improve the LSC with a new forward-slicing technique and additional out-of-order techniques that provide high performance with high efficiency.