Miss-Criticality

Dnr:

SNIC 2016/7-63

Type:

SNAC Small

Principal Investigator:

Mehdi Alipour

Affiliation:

Uppsala universitet

Start Date:

2017-06-21

End Date:

2018-01-01

Primary Classification:

10201: Datavetenskap (= Datalogi)

Webpage:

Allocation

Abstract

Out of order CPU architecture tries to cover cache miss cycles by executing instructions out of order program. Even using wide-way superscalar pipelines still there are some cache misses that can stall execution and block instruction committing as well. These misses can be called critical misses. In this experiment we will explore how many of cache misses are critical for an out of order CPU.