Energy-efficient memory system design

Dnr:

SNIC 2017/1-67

Type:

SNAC Medium

Principal Investigator:

David Black-Schaffer

Affiliation:

Uppsala universitet

Start Date:

2017-03-01

End Date:

2018-03-01

Primary Classification:

10206: Datorteknik

Secondary Classification:

10202: Systemvetenskap

Webpage:

http://www.it.uu.se/research/group/uart/hardware_optimization#energy_efficient_caches

Allocation

Abstract

Computer systems today spend nearly half of their energy on data movement, both within the processor and between the CPU and main memory. This research project aims to tackle this problem by investigating techniques to make the memory system more intelligent and thereby more power-aware. Our initial work in this area has developed novel techniques for power-efficient cache, data movement, and data placement. We have developed new techniques to model the interactions of graphics workloads in full-system simulation. These new techniques allow us to go beyond existing research that has focused only on compute workloads. In this project we will investigate the behavior of those systems and develop new techniques for optimizing memory system performance with large DRAM caches.