Computer systems today spend nearly half of their energy on data movement, both within the processor and between the CPU and main memory. This research project aims to tackle this problem by investigating techniques to make the memory system more intelligent and thereby more power-aware. Our initial work in this area has developed novel techniques for power-efficient cache, data movement, and data placement. In our first SNIC proposal we extended this work to evaluate more complex multicore benchmarks. Moving forward we will extend this work to even more detailed full-system integration (GPUs and modeling contention in the memory system), and continue our work on micro architectural integration of the pipeline and memory system and system-level integration of the OS/application and the memory system.