Number of in fight instructions in Out of Order processors is one the most important issues. Basically having more in fight instructions in Reorder Buffer (ROB) can improve dynamic scheduling as a key feature of superscalar processors. To have more instructions in ROB at least it is necessary to have larger ROB and more physical registers. Having larger ROB and many registers are very costly. In this project will focus on efficient register retirement as an idea to improve performance with same amount of budget for ROB size and number pf registers.